1. Field of the Disclosure
The present disclosure generally relates to an electronic memory and, more particularly, to providing a test pattern of pseudo random bit sequence (PRBS) during calibration of a delay locked loop (DLL) and during memory testing.
2. Brief Description of Related Art
Memory devices are widely used in many electronic products and computers to store data. A memory device includes a number of memory cells, each cell storing one bit of data. The data stored in the memory cells can be read during a read operation.
One type of memory device includes a reference signal to accompany data signals during a read operation. The reference signal, commonly known as a “strobe,” is used to track the output timing of the data signals read from the memory cells. In some traditional memory devices, the strobe signal is generated or turned on only during a read operation so as to enable downstream latching circuits (or flip-flops) to properly latch the data read from the memory cells. When a strobe is received in phase with the data it is latching, the strobe is preferably centered in the middle of the data so as to allow the latching circuits to more accurately time the latching operation. The centering of the strobe signal is generally done through a delay locked loop (DLL), which delays the strobe so that the latching edge of the strobe hits a flip-flop when the middle of the data window hits that flip-flop. The DLL, in turn, has to be calibrated to provide appropriate delay to the strobe signal during a data read operation. Current DLL calibration methods store very limited and generic test patterns in the memory's on-chip BIOS (basic input/output system). One such 16-bit generic test pattern is A5A5h for switching a bus to which the memory is connected during a data write/read operation. Current calibration methods switch only the whole bus with such a generic test pattern. That is, current calibration methods switch every bit line on the bus common-mode, i.e., with the same test pattern. A problem with this approach is that a high speed memory bus is rarely at a 100% usage, and the current methods of calibrating a DLL from the memory BIOS may not result in a very good representation of the bus under worst case switching conditions. Also, in the current methods, the BIOS may have limited control over the bus and over the individual bits or bytes on the bus.
As the current methods do not allow for the DLL calibration of each memory device under the worst case SSO (Simultaneous Switching Outputs) and cross-talk conditions on the bus, it is desirable to devise a method that provides memory test patterns to calibrate the DLL for each bit of each memory device for SSO, cross-talk, data routing mismatch and data loading mismatch. It is also desirable to allow a memory manufacturer to optimize the memory test patterns for each memory device so as to increase the accuracy of data read from the memory.